Transcription

Xilinx Power EstimatorUser GuideUG440 (v2018.1) April 4, 2018

Revision HistoryThe following table shows the revision history for this document.SectionRevision Summary04/04/2018 Version 2018.1Using Soft-Decision FEC (SD-FEC) Sheet and UsingRFADC-DAC SheetAdded SD-FEC and RFADC-ADC sheets informationSetting Clocks for Zynq UltraScale PS SheetAdded information on how to use the PS Tab for ZynqUltraScale MPSoC and RPU/APU% loadMemory Generator Wizard and the Block RAMSheet (Block Memory)Added notes on Block RAM Configuration ModesUsing Other Sheets (7 Series, Zynq-7000 AP SoC,UltraScale and UltraScale Devices)Added a note on VCU power including both static and dynamicpowersEstimating HBM Power (HBM Sheet)Added information on HBM sheet available for VirtexUltraScale HBM devices.Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback2

Table of ContentsChapter 1: OverviewIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Getting Started with XPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Definitions/Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Using XPE User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15XPE Cell Color-Coding Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Using the Summary Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Using the XPE Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Using XPE Wizards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Chapter 2: Specifying and Managing ClocksSpecifying Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Using the Clock Management Resource Sheets (DCM, PMCD, PLL, MMCM, Clock Manager) . . . . 48Chapter 3: Using Xilinx Power Estimator SheetsOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the Logic Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the IP Manager Sheet (7 Series, Zynq-7000 AP SoC, UltraScale and UltraScale Devices). .Using an I/O Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the Block RAM (BRAM) Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the DSP Sheet (MULT, DSP48). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the Transceiver Sheets (GTP, GTX, GTH, GTY, GTZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the TEMAC Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the PCIe Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using PPC440 (PowerPC) Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using the PS Sheet (Zynq-7000 AP SoC and Zynq UltraScale MPSoC) . . . . . . . . . . . . . . . . . . . . . .Using Soft-Decision FEC (SD-FEC) Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using RFADC-DAC Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Estimating HBM Power (HBM Sheet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using Other Sheets (7 Series, Zynq-7000 AP SoC, UltraScale and UltraScale Devices) . . . . . . . . .Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback5151545763686975767677889092953

Chapter 4: Exchanging Power InformationOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Exporting Settings from XPE to XPower Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Importing Results from XPower Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Importing Results from Vivado Power Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Importing and Exporting the Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Importing Data into XPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Exporting XPE Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Chapter 5: Automating XPEOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using Named Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using Formulas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using Visual Basic Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Scripting XPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108108112113115Chapter 6: Using Snapshots and Graph SheetsUsing the Power Comparison Snapshots Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Using Graph Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Appendix A: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback1251251251261271284

Chapter 1OverviewIntroductionThe Xilinx Power Estimator (XPE) spreadsheet is a power estimation tool typically used inthe pre-design and pre-implementation phases of a project. XPE assists with architectureevaluation, device selection, appropriate power supply components, and thermalmanagement components specific for your application.XPE considers your design resource usage, toggle rates, I/O loading, and many other factorswhich it combines with the device models to calculate the estimated power distribution.The device models are extracted from measurements, simulation, and/or extrapolation.The accuracy of XPE is dependent on two primary sets of inputs: Device utilization, component configuration, clock, enable, and toggle rates, and otherinformation you enter into the tool Device data models integrated into the toolFor accurate estimates of your application, enter realistic information which is as completeas possible. Modeling a certain aspect of the design too conservatively or without sufficientknowledge of the design can result in unrealistic estimates. Some techniques to drive theXPE to provide worst-case estimates or typical estimates are discussed in this document.XPE is a pre-implementation tool for use in the early stages of a design cycle or when theRegister Transfer Level (RTL) description is incomplete. After implementation, the XPowerAnalyzer (XPA) tool (in the ISE Design Suite) or Report Power (in the Vivado Design Suite)can be used for more accurate estimates and power analysis. For more information aboutXPA, see the XPower Analyzer Help [Ref 1]. For more information about the Vivado poweranalysis feature, see the Vivado Design Suite User Guide: Power Analysis and Optimization(UG907) [Ref 2].XPE is a spreadsheet, so all Microsoft Excel functionality is fully retained in the writable orunprotected sections of the spreadsheet. XPE has additional functionality oriented towardsease of use. The drop-down menus and the comment-enabled cells are helpful features toguide you.Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback5

Chapter 1:OverviewX-Ref Target - Figure 1-1Figure 1-1:Xilinx Power Estimator SpreadsheetThe XPE spreadsheet also includes the Quick Estimate Wizard, the Memory InterfaceConfiguration Wizard, the Memory Generator Wizard (for block memory and distributedmemory), and the Transceiver Configuration Wizard. These wizards help novice and expertusers to quickly enter the important configuration parameters, which will then generaterelevant lines in the I/O, Logic, Block RAM (BRAM), Transceiver, and Other sheets, helpingwith accurate power estimation.Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback6

Chapter 1:OverviewVIDEO: The Vivado Design Suite QuickTake Video Tutorial: Using the Xilinx Power Estimator shows howthe Xilinx Power Estimator can help you determine power and cooling specifications for AllProgrammable SoC and FPGA designs early in the product’s design cycle, often even before the logicwithin the All Programmable SoC or FPGA has been designed.Getting Started with XPEOpening XPE1. XPE requires Microsoft Excel 2003 or later to be installed.Table 1-1:Supported versions of Microsoft Excel for XPEDevice FamilySupported Excel versionUltraScale Microsoft Excel 2007, 2010, 2013, 2016 and Office 365(.xlsm)UltraScale Microsoft Excel 2007, 2010, 2013, 2016 and Office 365(.xlsm)7series and Zynq -7000Microsoft Excel 2007, 2010, 2013, 2016 and Office 365(.xlsm)OpenOffice and Google Docs spreadsheet editors are not supported in this release ofXPE.2. Download the latest available spreadsheet for your targeted device. The XPEspreadsheets are available at the Power Efficiency web page.3. Make sure your Microsoft Excel settings allow macro executions. XPE uses severalmacros built into the XPE spreadsheet. Microsoft Excel 2010 or 2013 or 2016/Office 365 - The following steps arerequired:a.From the XPE spreadsheet select File Options.b.In the Excel Options dialog box, click Trust Center.c.In the Trust Center dialog box, click Trust Center Settings and select the MacroSettings tab.d.Select Enable all macros, then click OK.e.Reopen the XPE spreadsheet. Microsoft Excel 200 7 - The following steps are required:a.From the Microsoft Office button select Excel Options.b.In the Options dialog box, click Trust Center.c.In the Trust Center dialog box, click Trust Center Settings, and select the MacroSecurity tab.Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback7

Chapter 1:Overviewd.Select Enable all macros, then click OK.e.Open or, if already open, reopen the XPE spreadsheet.IMPORTANT: If you save an Excel 2007 or later spreadsheet as an .xlsx file (Excel Workbook) you willlose the macro capability and render XPE nonfunctional. You will be warned of this if you try to save asan .xlsx file. Microsoft Excel 2003 - By default, the macro security level is set to High, whichdisables macros. To change the macro security level, follow these steps (actualmenu names will vary with language of Microsoft Excel):a.On the Tools menu, point to Macro and click Security.b.In the Security dialog box, click the Security Level tab.c.Select Medium, then click OK.d.Open or, if already open, reopen the XPE spreadsheet.e.When prompted whether to enable or disable macros, click Enable Macros.IMPORTANT: On Windows, make sure your language is set to English. Select Control Panel Clock,Language, and Region Region and Language, and set Format to English.User Input RequirementsPower estimation for programmable devices like FPGAs is a complex process, because it ishighly dependent on the amount of logic in the design and the configuration of that logic.To produce accurate estimates, the power estimation process requires accurate inputvalues, such as resource utilization, clock rates, and toggle rates. To supply the minimuminput that will allow XPE to estimate power with reasonable accuracy, you need thefollowing: A target device-package-grade combination A good estimate of resources you expect to use in the design (for example, flip-flops,look-up tables, I/Os, block RAMs, DCMs or MMCMs, and PLLs.) The clock frequency or frequencies for the design An estimate of the data toggle rates for the design The external memory and transceiver based interfaces with their data rates for thedesign The thermal environment in which the design will be operatingAs a general rule, input as much information about your design as available, then leave theremaining settings to default values. This strategy will allow you to determine the devicepower supply and heat dissipation requirements.Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback8

Chapter 1:OverviewTIP: Use Excel formulas to link different cells together. For example, type ' CLOCK!E10' in the Clockcells of the Logic sheet, which lists the resources driven by this clock domain.XPE Calculations and ResultsXPE uses your design and environmental input, then combines this information with thedevice data model to compute and present an estimated distribution of the power in thetargeted device.XPE presents multiple views of the power distribution. Power by Voltage Supplies - For each required voltage source, this information isuseful to select and size power supply components, such as regulators. Supply powerincludes both off-chip and on-chip dissipated power. Power by User Logic Resources - For each type of user logic in the design, XPE reportsthe expected power. This allows you to experiment with architecture, resources, andimplementation trade-off choices to remain within the allotted power budget. Thermal Power - XPE lets you enter device environment settings and reports thermalproperties of the device for your application, such as the expected junctiontemperature. With this information you can evaluate the need for passive or activecooling for your design.The Summary sheet in XPE shows the total power for the device. Other sheets showusage-based power. Leakage within the unused portion of the considered resource (if any)is not shown.IMPORTANT: In XPE, the power number cells are configured to display values with three decimal places(for example, 0.000). The rounding of numbers with three precision is based on Microsoft Excelbehavior. Values less than 1mW are displayed as 0.000W. You can copy a cell and paste it into the Usersheet to see the actual value with precision adjusted.Definitions/TerminologySupported Device FamiliesSeparate spreadsheets are available depending on the targeted architecture. Thesespreadsheets are updated when new device data become available or when new featuresare added to XPE. UltraScale devices Kintex UltraScale Virtex UltraScale Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback9

Chapter 1: OverviewZynq UltraScale -Zynq UltraScale MPSoC-Zynq UltraScale RFSoC-Zynq UltraScale MPSoC AutomotiveUltraScale devices Kintex UltraScale Virtex UltraScale Kintex UltraScale Automotive7 Series devices and Zynq-7000 AP SoCs Artix -7, Artix-7 Automotive grade, and Artix-7 Defense grade Kintex-7 and Kintex-7 Defense grade Virtex-7 and Virtex-7 Defense grade Zynq -7000, Zynq-7000 Automotive grade, and Zynq-7000 Defense grade Spartan -7Virtex-6 and Virtex-5 devices Virtex-6 , Virtex-6 Low Power, and Virtex-6Q Defense grade Virtex-5 , Virtex-5Q Defense grade, and Virtex-5QV Space grade Virtex-4 Spartan -6 and Spartan-3A – This spreadsheet includes all sub-families, includingSpartan-6 Lower Power, Spartan-6 Automotive, Spartan-6Q Defense-grade,Spartan-3AN, and Spartan-3A DSP Spartan-3E Spartan-3IMPORTANT: Download the latest available spreadsheet from the Xilinx Power Estimator (XPE) webpage.Device Model AccuracyThe accuracy of the characterization data existing in the tool is reflected by accuracydesignations in the Characterization field on the Summary sheet of XPE. For most devices,the history of the accuracy designation is also displayed in the Release sheet. The accuracydesignations are Advance, Preliminary, and Production.Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback10

Chapter 1:OverviewAdvanceThese specifications are based on simulations only and are typically available soon after thedevice design specifications are frozen They are subject to change as siliconcharacterization data becomes available. Advance data accuracy is considered lower thanthe Preliminary and Production data.PreliminaryThe data integrated into XPE with this designation is based on complete early productionsilicon. Almost all the blocks in the device fabric are characterized. Data for most of thededicated blocks like TEMAC and PCIe block are also characterized and integrated intoXPE. The accuracy of power reporting is improved compared to Advance data.ProductionThe data integrated into XPE with this designation is released after enough productionsilicon of a particular device family member has been characterized to provide full powercorrelation over numerous production lots. Characterization data for all blocks in the devicefabric is included.Total PowerThe total device power is calculated as follows:Total devices power Device Static Design Static Design DynamicThe power estimates are modeled to account for temperature and voltage sensitivity.Ambient temperature and regulated voltage on the system can be keyed into theappropriate cells provided for that purpose.Device Static PowerAlso referred to as Leakage. Device static represents the transistor leakage power when thedevice is powered and not configured.Design Static PowerDesign static represents the additional power consumption when the device is configuredbut there is no switching activity. It includes static power in I/O DCI terminations, clockmanagers, and so forth.For design static power calculations, XPE starts by assuming a blank bitstream. To add yourdesign elements (for example, Logic, I/Os, BRAMs, Clock Managers) to the design staticpower calculations, you must enter the resource utilization and configuration in the XPEresource sheets applicable to the design. Any I/O termination should be set to match theXilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback11

Chapter 1:Overviewboard and the design. For any clock managers, enter a small clock frequency to indicateusage. Enter or leave clock frequency values 0 on other resource sheets.Note: For maximum process, the static power in a device should never exceed the reported valuesin the tool.Design Dynamic PowerDesign dynamic represents the additional power consumption from the user logicutilization and switching activity.Activity RatesXPE shows values for these types of activity rates: Toggle Rates Signal RatesToggle RatesProviding accurate toggle rates in the various XPE sheets is essential to get quality powerestimates. This information, however, might not be readily available at the stage in thedesign cycle where you enter data in XPE. Activity might be refined as the design gets moredefined. Following are guidelines you can follow to help you enter design toggle activity. For synchronous paths, toggle rate reflects how often an output changes relative to agiven clock input and can be modeled as a percentage between 0–100%. The max datatoggle rate of 100% means that the output toggles every active clock edge. Forexample, consider a free running binary counter with a 100MHz clock. For the LeastSignificant Bit you would enter 100% in the Toggle Rate column, because this bittoggles every rising edge of the clock. For the second bit you would enter 50%,because this bit toggles every other rising edge of the clock. When data changes twiceper clock cycle, enter 200% for the toggle rate. For non-periodic or event-driven portions of designs, toggle rates cannot be easilypredicted. An effective method of estimating average toggle rates for a given design isto segregate the different sections of the design based on their functionality orhierarchy and estimate the toggle rates for each of the sub-blocks. An average togglerate can then be arrived at by calculating the average for the entire design or hierarchy.Most logic-intensive designs work at around 12.5% average toggle rate, which is thedefault toggle rate setting in XPE.It has been observed that designs with random data patterns as input generally havetoggle rates between 10%-30%. However, designs with a lot of glitch logic can havetoggle rates as high as or even higher than 50%. Glitch logic is generally classified ascombinatorial functions which have a high probability of the output changing when anyone input changes, such as XOR gates or unregistered arithmetic logic (i.e. adders).Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback12

Chapter 1:OverviewFunctions that use large amounts of such logic, such as error detection/correctioncircuitry, might exhibit higher toggle rates due to this. Designs with large amounts ofcontrol path logic, such as embedded designs, on average have lower toggle rates dueto large sections of logic being inactive at any given time during operation.In summary, the primary factors that have an appreciable impact on the toggle rate of adesign are: Input data pattern - Random data pattern versus known patterns have an impact on thetoggle rate. Control signals - Use or lack of control signals such as reset and clock enables. Design logic - High glitch XOR/CARRY logic, a highly pipelined design, or an embeddeddesign have an impact on the toggle rate.General guidelines for the toggle-rates of Ex-OR (XOR) circuitXOR logic cones contain more glitches and as the number of logic levels increases, theglitch count keeps increasing. However, it does have a saturation point. In a non-glitchactivity, the saturation point will be at 50% toggle rate (at 3 to 4 levels of XOR tree)In XOR logic, toggle rates depend on the circuit topology. Number of glitches depends onthe exact depth and width of an XOR tree. Different XOR logic tree depth levels givedifferent results.Example:Maximum XOR Toggle rate in a user combinational logic assuming 1024 wide XOR with adepth of 10 levels is as follows: 815% - Worst input 254% - Random inputMaximum XOR Toggle rate in user combinational logic assuming 32 wide XOR with a depthof 5 levels: 516% - Worst input 114% - Random inputIMPORTANT: In all the sheets which do not have a dedicated Clock Enable column make sure youscale the toggle rate to account for any signal which gates this logic. For example, if the data togglerate is modeled at 50% but the synchronizing clock is enabled 50% of the time, the resulting toggle rateshould be 25% (50% x 50%).Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback13

Chapter 1:OverviewIMPORTANT: To appreciate what 100% toggle rate means, think of a constantly enabled toggleflip-flop (TFF) whose data input is tied High. The T-output of this flip-flop toggles every clock edge.Very few designs could possibly have an average toggle rate that high (100%).Note: The I/O sheet has a column to specify signal Data Rate. Make sure you adjust the ToggleRate and Data Rate columns accurately. For example, on an input signal which toggles on bothedges of the clock you would enter Toggle Rate 200% and Data Rate DDR (Dual Data Rate).Signal RatesSignal rate defines the number of millions of transitions per second (Mtr/s) for the elementconsidered. This is a read-only column that appears on some of the XPE sheets (forexample, the Logic, I/O, DSP, and Block RAM sheets). The general equation to calculatesignal rate is:Signal Rate (Mtr/s) Clock Frequency (Mhz) * Effective Toggle Rate (%)FanoutFanout defined in XPE is similar to the fanout reported by the synthesis tool and can differfrom the fanout reported by the implementation tool. This difference is expected becausefanout will vary with placement and packing of the logic. In XPE, fanout represents the number of individual loads or logic elements theconsidered element is connected to (LUTs, flip-flops, block RAM, I/O flip-flops,distributed RAM, and shift registers). In the Vivado IDE, fanout represents the number of SLICEs the considered net is routedto. A SLICE typically contains multiple logic elements and you generally do not controlpacking of the different elements into SLICEs. XPE algorithms will estimate this packingbefore calculating the power.Effective Θ JA (C/W)This coefficient defines how power is dissipated from the Xilinx device to the environment(device junction to ambient air). Typically this option is calculated by XPE, taking intoaccount, among other things, the different environment parameters in the Settings panelof the Summary sheet. Entering a value in this field will override XPE calculations. Use thisoption if you have calculated this parameter by thermal simulations. You might also want touse this feature to factor out environmental parameters when analyzing power differenceswith another spreadsheet in which environment settings have been set differently.ΘSA (C/W)Θ SA represents the heat sink to ambient air thermal resistance. By default XPE obtains thisvalue from a representative selection of heat sink data matched to the device package,Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback14

Chapter 1:Overviewcombined with the Heat Sink value you set (Low Profile, Medium Profile, or High Profile)and the Airflow value you set. The value used by XPE is shown in the Θ SA field on theSummary sheet.If you have the ΘSA information for your system you can enter your specific value. First setthe Heat Sink drop-down menu on the Summary sheet to Custom, then enter your ΘSAvalue.ΘJB (C/W)Θ JB represents the device junction to board thermal resistance. By default XPE estimatesthe junction to board thermal resistance based on standard JEDEC four-layermeasurements. If you have done thermal simulations of your system you can enter yourown specific value. First set the Board Selection drop-down menu on the Summary sheetto Custom, then enter your ΘJB value.Junction Temperature ( C)This user defined field forces the value of the device junction temperature. XPE then adjuststhe ambient temperature to meet the specified junction temperature. This option could beused when you need to work backward from a known or assumed worst case junctiontemperature and define the environment that would ensure this temperature is notexceeded.The Xilinx Analog to Digital Converter (XADC) component is included in many of the currentdevices. As the XADC measures the Junction Temperature, you should wait for the value tostabilize before and after configuring the device.Using XPE User InterfaceXPE has the following sheets: The Summary sheet lets you enter and edit all device and environment settings. Thissheet also displays a summary of the power distribution and provides buttons toimport data into XPE, export results, and globally adjust settings. Other sheets allow you to enter usage and activity details for the different resourcetypes available in the targeted device, for example, I/O, Block RAM (BRAM), andMulti-Gigabit Transceivers (MGTs). These sheets report design power based on theresource usage. Resource leakage power is shown on the Summary sheet.TIP: XPE is intended to be intuitive to the novice spreadsheet-user. For information about a cell in thespreadsheet, move the mouse over the comment indicators (red triangle at the top right corner of thetitle cells) to read the relevant notes for the intended use (see Figure 1-2).Xilinx Power Estimator User GuideUG440 (v2018.1) April 4, 2018www.xilinx.comSend Feedback15

Chapter 1:OverviewX-Ref Target - Figure 1-2Figure 1-2:Comment Indicators and CommentXPE Cell Color-Coding SchemeTo simplify data entry and review, the XPE cells are color coded. A color Legend appears atthe bottom of the Summary sheet (see Figure 1-3).X-Ref Target - Figure 1-3Figure 1-3:Color Legend (Summary Sheet)A description of the spreadsheet color-coding scheme is provided in Table 1-2.Table 1-2:XPE Cell Color-C

Download the latest available spreadsheet for your targeted device. The XPE . 2010, 2013, 2016 and Office 365(.xlsm) 7series and Zynq -7000 Microsoft Excel 2007, 2010, 2013, 2016 and Office 365(.xlsm) Send Feedback. Xilinx Power Estimator User Guide www.xilinx.com 8 . includes both off-chip and on-chip dissipated power.