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QuickBoot Implementation DetailsIn summary, the QuickBoot configuration method quickly determines which bitstream to load asthe first step in the configuration process via the critical switch word. The FPGA then proceedswith a standard configuration process from the selected bitstream area.QuickBoot Flash Programming MethodThe update bitstream programming procedure determines the robustness of the QuickBootsolution. These conditions are required of the flash programming procedure for reliableQuickBoot configuration:1. The critical switch word must be turned OFF before attempting any modification of theupdate bitstream. Changing the critical switch word to any value other than the exact ONvalue turns the switch OFF.2. The critical switch word is turned ON only after the update bitstream has been verified tohave been correctly programmed. The switch can only be turned ON by setting the criticalswitch word to the exact, unique ON value.3. The golden image and part two of the QuickBoot header must never be modified to ensuretheir integrity for all cases.Because the QuickBoot configuration method configures from the update bitstream image onlywhen the critical switch word is ON, requirements 1 and 2 ensure that the FPGA neverexecutes the warm boot jump sequence to the update bitstream area when there is anypossibility that the update bitstream area does not contain a correctly programmed bitstream.Requirement 3 ensures that the golden bitstream can be safely loaded whenever the criticalswitch word is OFF or that the warm boot jump sequence correctly directs the FPGA to theupdate bitstream.QuickBoot Flash Programming AlgorithmThe QuickBoot flash programming algorithm is:1. Erase the sub-sector or block containing the critical switch word to turn OFF the switch.2. Erase the sectors or blocks of the update image area.3. Program the update bitstream into the update image area.4. Verify that the update image has been programmed correctly.5. Program the critical switch word to its exact ON value to turn the switch ON, but only afterthe update image has been verified.QuickBootImplementationDetailsThe QuickBoot implementation relies on these elements: Critical Switch Word Flash Memory Overview and QuickBoot Flash Memory Component Mapping Bitstream Image Size and Flash Memory Size Selection QuickBoot Configuration Time QuickBoot Verification of the Update ImageCritical Switch WordThe critical switch word is a special word value. The switch is considered to be ON only whenthe critical switch word location contains an exact, predetermined value. The existence oromission of the exact critical switch word value dictates whether or not the FPGA configurationlogic executes the warm boot jump sequence.An understanding of the FPGA bitstream and of the FPGA’s built-in configuration logic isrequired for understanding the operation of the critical switch word and its special ON value.XAPP1081 (v1.3) March 18, 2014www.xilinx.com5

QuickBoot Implementation DetailsThe Xilinx FPGA is configured via a bitstream (.bit file) comprising a sequence of 32-bitwords. The 32-bit words are one of these types: Bus width auto detection word that the FPGA uses to automatically detect the parallelconfiguration data bus width at the beginning of a BPI and SelectMAP mode configuration. Sync word that marks the beginning of the bitstream and synchronizes the configurationlogic to a 32-bit boundary of the packets that follow the sync word for all configurationmodes. Packet header word that specifies a register and data word count for writing data to aregister. Packet command or data words for each packet. For a packet that specifies a write to theconfiguration command register, the word is a command such as the IPROG command.For a packet that specifies a write to WBSTAR, the data word includes the warm boot jumpaddress.Note: For details about the bitstream bus width auto detect words, sync word, and packets see the“Configuration Details” chapter in 7 Series FPGAs Configuration User Guide [Ref 1].All bitstreams generated by Xilinx design tools are composed of the following in sequentialorder:1. bus width auto detect words2. sync word3. data packets that define the FPGA configurationWhen the FPGA reads data from a BPI flash memory, the FPGA configuration logic remains inits first stage until it detects a 0xBB data value from the first word of the bus width auto detectpattern on its D[0:7] pins. During the initial search for the bus width auto detect pattern, theFPGA effectively ignores all incoming data until it recognizes a valid bus width auto detectpattern. Thus, for BPI mode configuration, the first word of the bus width auto detect pattern0x000000BB is the critical switch word for the QuickBoot method. In terms of the QuickBootcritical switch word, the remaining stages of the FPGA configuration logic are not turned ONuntil after the bus width auto detect pattern is found.In SPI mode, the FPGA does not use bus width auto detect logic.When the FPGA reads data from an SPI flash memory, the FPGA configuration logic remainsin its first stage monitoring the incoming data for the sync word 0xAA995566 to synchronizeitself to the boundary of the 32-bit words of the incoming bitstream. During the initial search forthe sync word, the FPGA effectively ignores all incoming data until it recognizes the sync word.Thus, for SPI mode configuration, the sync word is the critical switch word for the QuickBootmethod. In terms of the QuickBoot critical switch word, the remaining stages of the FPGAconfiguration logic are not turned ON until after the sync word is found.Table 1 summarizes the exact value that enables the critical switch word to be turned ON foreach configuration mode.Table 1: Critical Switch Word ON ValueConfiguration ModeCritical switch word (32-bit value)BPI ModeSPI Mode0x000000BB (1)0xAA995566Notes:1.XAPP1081 (v1.3) March 18, 2014Due to bit and byte swapping, the critical switch word for a BPI flash hexadecimal data (MCS) fileappears as 0x0000DD00 within the MCS file.www.xilinx.com6

QuickBoot Implementation DetailsFlash Memory Overview and QuickBoot Flash Memory ComponentMappingImplementation of the QuickBoot flash programming algorithm requires knowledge of the NORflash memory architecture and operations. In particular, the QuickBoot flash memorycomponents must be mapped to specific flash memory regions, and the QuickBoot algorithmprocedures must be mapped to the available flash operations for those specific regions.Flash Memory Architecture and OperationsA NOR flash memory contains a linear array of data words or data bytes. The linear array issegmented into erasable blocks or sectors. For some NOR flash memories, the sectors arefurther segmented into subsectors. See the appropriate NOR flash memory data sheet for thesegments and their sizes [Ref 2] [Ref 3].Reprogramming a NOR flash memory with new data values requires a two-step process:1. An erase operation to reset all data bits of a selected segment to a 1 state.2. A program operation to change data bits only from a 1 state to a 0 state.The erase operation can be performed on a block, sector, or sub-sector. That is, all data wordsor bytes within the specified segment are erased via each erase operation. The programoperation can be performed on a single word or byte.Note: Usually for speed, each program operation programs a buffer of words or page of bytes.General Mapping of QuickBoot Components Within Flash MemoryBecause modification of the flash memory requires an erase operation and because an eraseoperation affects an entire flash memory segment, the flash memory segment architecturedictates the placement of the QuickBoot components within a flash memory:1. The QuickBoot header is placed in this sequence:a. QuickBoot header part 1, the critical switch word, is placed in its own erasablesegment.b.QuickBoot header part 2 follows part 1 but in a different flash segment than part 1.2. The golden bitstream image follows the QuickBoot header in the flash memory array.3. The update bitstream image is placed in its own erasable segments. The update imagedoes not share any erasable segments with the golden bitstream image.The critical switch word is placed within its own erasable segment such that the destructprocess, which is an erase operation, affects only the critical switch word. Similarly, the updateimage is placed in its own set of segments such that the reprogramming process does notaffect the golden bitstream image.Detailed Mapping of QuickBoot Components to BPI Flash MemoryA detailed map of the BPI flash memory contents for the QuickBoot solution in a Micron P30flash memory [Ref 2] is shown in Figure 5. The critical switch word is located at the end of thefirst erasable block, which is 65,536 (0x00010000) 16-bit words in size. The figure showsexamples of a good and bad update bitstream. In a good update bitstream, the area reservedfor the update bitstream contains a valid bitstream. In a bad bitstream, the area reserved for theupdate bitstream contains data that is in a corrupted, incomplete, or unknown condition.XAPP1081 (v1.3) March 18, 2014www.xilinx.com7

QuickBoot Implementation DetailsX-Ref Target - Figure 5Data LegendBlack Text Standard bitstream from design tools.Blue Text Data added by/for reference design.Red Text Unknown or don’t care data.Light-Red Background QuickBoot Header – two parts.Yellow/Gold Background “Golden” data image.Green Background “Update” data image.Blue Dashed Line FPGA read path, ignoring data.Blue Solid Line FPGA read path, executing commands.Green Line FPGA loading configuration.Flash26-bit WordAddressFlash Contents forGood Update(when updateimage/contentis verified GOOD)0x000000000xFFFFFFFF0xFFFFFFFF 0xFFFFFFFF0x0000FFFE0x000000BB(bus width autodetect 100180x001000000x001FFFFEGOLDEN BITSTREAM: 0x000000BB0x11220044 0xAA995566 bitstream packets 0xFFFFFFFF0xFFFFFFFF 0xFFFFFFFFUPDATE BITSTREAM: 0x000000BB0x11220044 0xAA995566 bitstream packets 0xFFFFFFFF0xFFFFFFFF 0xFFFFFFFFFlash Contentsfor Bad Update(when updateimage/content isNOT 0000F0x200000000x200000000x20000000GOLDEN BITSTREAM: 0x000000BB0x11220044 0xAA995566 bitstream packets 0xFFFFFFFF0xFFFFFFFF 0xFFFFFFFF? Update-CRC32 High-Level Block Description(Descriptions of the three major blocks ofdata within the flash memory)Detailed Description of Data Content(Details for each data word orsignificant data group)Eraseable Block 0:Contains padding of dummy (0xFFFFFFFF) words, plus the"critical switch word" (0x000000BB) at word address0x000FFFE. If this switch word is NOT present, the FPGAignores the following data while searching for the first0x000000BB word.Second word of bus width auto detect sequenceDummy wordDummy wordBitstream Sync WordBitstream NOOP packetBitstream WRITE to warm boot start (WBSTAR) packetPacket data: warm boot start address 0x00200000Bitstream WRITE to COMMAND register packetPacket data: IPROG command.Bitstream NOOP packetBitstream NOOP packetBitstream NOOP packetThe "golden" bitstream, a standard bitstream from Xilinxdesign tools.NOTE: All standard bitstreams begin with a bus width autodetect sequence and sync word.Dummy pad words to fill from end of the "golden" bitstreamto the end of the "golden" image.The "update" bitstream, a standard bitstream from Xilinxdesign tools.NOTE: All standard bitstreams begin with a bus width autodetect sequence and sync word.?Dummy pad words to fill from end of the "update" bitstreamto the end of the "update" image, minus the last 4 bytes thatare reserved for the CRC32.?32-bit reciprocal of CRC32 for all bytes in the "update" imagearea from addresses 0x00100000 to 0x001FFFFE.QUICKBOOT HEADER - PART 1: THE CRITICAL SWITCH WORD:This is the first and smallest erasable flash block. This block contains the first bus widthauto detect word, which enables an FPGA to begin its process of interpreting the packetsthat follow or, if not present, causes the FPGA to ignore the words that follow while itcontinues to search for the first bus width auto detect word.QUICKBOOT HEADER - PART 2: THE WARM BOOT JUMP SEQUENCE:This section of the QuickBoot header includes the remainder of the bus width autodetect words to complete the bus width auto detect process, a sync word to synchronizethe configuration logic to the 32-bit boundary of the 32-bit packet words, and the warmboot jump sequence. The warm boot jump sequence is a series of bitstream packetsthat write an address to the warm boot start address register (WBSTAR) andcommand and address, plus an IPROG command. Only if the FPGA configurationlogic sees the first bus width auto detect word in the first part of the header does theFPGA interpret these packets and execute this warm boot sequence. Otherwise,the FPGA configuration logic ignores these data words while it continues its search forthe first bus width auto detect word.THE "GOLDEN" IMAGE:The "golden" image contains the known-good, "golden" design bitstream(s).If the QuickBoot header did not contain the first bus width auto detect word, theFPGA configuration logic continues searching through the flash and finds the first buswidth auto detect word in this golden bitstream. Thus, configuration can start here.The "golden" image contains:1. A standard bitstream, which is the "golden" design.2. Dummy pad words (0xFFFFFFFF) to fill the area between the end of the "golden"bitstream and the end of the "golden" image/area.THE "UPDATE" IMAGE/AREA:Updated design bitstreams are programmed into this "update" area, which is alignedto erasable sector boundaries.The "update" image/area contains:1. A standard bitstream, which is the "updated" design.2. Dummy pad words (0xFFFFFFFF) to fill the area between the end of the "update"bitstream and the Update-CRC32 at the end of the "update" image/area.4. Update-CRC32 "Complemented" CRC32 value for all bytes in the "update"image area, except for the last four bytes, which are reserved for the 32-bit Update-CRC32 .X1081 05 041513Figure 5:QuickBoot BPI Flash Memory Map for Good and Bad Update ImagesNote: The addresses shown in Figure 5 for the update image are for a bitstream that can fit in a 16 Mbspace. The update bitstream image addresses can be different for different sized FPGAs. See thereference design files for an Excel version of this information.For the good update example, the critical switch word location contains the first bus width autodetect word 0x000000BB. The FPGA configuration logic goes through this sequence for thegood update example:1. Begins the bus width auto detect sequence.2. Executes the warm boot jump sequence that follows in part 2 of the QuickBoot header.3. Concludes by loading the update bitstream.For the bad update example, the critical switch word location does not contain the first buswidth auto detect word. Therefore, the FPGA configuration logic goes through this sequence forthe bad update example:1. Continues to search for the bus width auto detect words, ignoring part 2 of the QuickBootheader.2. Finds the standard bus width auto detect words that begin the golden bitstream.3. Concludes by loading the golden bitstream.The update bitstream is located within its own set of erasable blocks. The start of the updatebitstream is aligned to the beginning of its first erasable block at word address 0x00100000.XAPP1081 (v1.3) March 18, 2014www.xilinx.com8

QuickBoot Implementation DetailsNote: The addresses of the update bitstream image for a specific implementation can be different fromthat shown in Figure 5 because the update image depends on the bitstream size.Detailed Mapping of QuickBoot Components to SPI Flash MemoryThe mapping of the QuickBoot components to SPI flash memory is similar to the mapping toBPI flash memory, except for a difference in the critical switch word. In SPI mode, the FPGAconfiguration logic skips its bus width auto detect stage and instead first begins searching forthe sync word. Therefore, the bus width auto detect words are omitted from the QuickBootheader, and the QuickBoot header for SPI flash memory begins with the sync word as thecritical switch word.Figure 6 shows a detailed map of the SPI flash memory contents for the QuickBoot solution ina Micron N25Q flash memory [Ref 2]. The critical switch word is located at the end of the firsterasable sub-sector, which is 4,096 (0x00001000) 8-bit bytes in size.X-Ref Target - Figure 6Data LegendBlack Text Standard bitstream from design toolsBlue Text Data added by/for reference designRed Text Unknown or don’t-care dataLight-Red Background QuickBoot Header - two partsYellow/Gold Background "Golden" data imageGreen Background "Update" data imageBlue dashed line FPGA read path, ignoring dataBlue solid line FPGA read path, executing commandsGreen line FPGA loading configurationFlash8-bit ByteAddressFlash Contents forGood UpdateFlash Contents forBad Update(when update image/contentis verified GOOD)(when update image/contentis NOT good)0x000000000xFFFFFFFF0xFFFFFFFF 0xFFFFFFFF0x00000FFC0xAA995566(sync 0000F0x200000000x200000000x20000000GOLDEN BITSTREAM: 0x000000BB0x11220044 0xAA995566 bitstream packets 0xFFFFFFFF0xFFFFFFFF 0xFFFFFFFFUPDATE BITSTREAM: 0x000000BB0x11220044 0xAA995566 bitstream packets 0xFFFFFFFF0xFFFFFFFF 0x20000000GOLDEN BITSTREAM: 0x000000BB0x11220044 0xAA995566 bitstream packets 0xFFFFFFFF0xFFFFFFFF 0xFFFFFFFF? Update-CRC32 Detailed Description of Data ContentHigh-Level Block Description(Details for each data word or significant data group)(Descriptions of the three major blocks of data within the flash memory)Eraseable Subsector 0:Contains padding of dummy (0xFFFFFFFF) words, plus the"critical switch word" (0xAA995566) at byte address0x0000FFC. If this switch word is NOT present, the FPGAignores the following data, while searching for the first0xAA995566 word.QUICKBOOT HEADER - PART 1: THE CRITICAL SWITCH WORD:This is the first and smallest erasable flash block (e.g., subsector). This blockcontains the sync word, which enables an FPGA to begin its process ofinterpreting the packets that follow or, if not present, causes the FPGA toignore the words that follow while it continues to search for the sync word.Bitstream NOOP packetBitstream WRITE to warm boot start (WBSTAR) packetPacket data: Warm boot start address 0x00200000Bitstream WRITE to COMMAND register packetPacket data: IPROG commandBitstream NOOP packetBitstream NOOP packetBitstream NOOP packetThe "golden" bitstream, a standard bitstream from Xilinxdesign tools.NOTE: All standard bitstreams begin with a bus width autodetect sequence and sync word.QUICKBOOT HEADER - PART 2: THE WARM BOOT JUMP SEQUENCE:The warm boot jump sequence is a series of bitstream packets that write anaddress to the warm boot start address register (WBSTAR) and commandand address, plus an IPROG command. Only if the FPGA configuration logicsees and synchronizes to the previous sync word does the FPGA interpretthese packets and execute this warm boot sequence. Otherwise, the FPGAconfiguration logic ignores these data words while it continues its search forthe sync word.Dummy pad words to fill from end of the "golden" bitstream tothe end of the "golden" image.The "update" bitstream, a standard bitstream from Xilinxdesign tools.NOTE: All standard bitstreams begin with a bus width autodetect sequence and sync word.?Dummy pad words to fill from end of the "update" bitstreamto the end of the "update" image, minus the last 4 bytes thatare reserved for the CRC32.?32-bit reciprocal of CRC32 for all bytes in the "update" imagearea from addresses 0x00200000 to 0x003FFFFB.THE "GOLDEN" IMAGE:The "golden" image contains the known good, "golden" design bitstream(s).If the QuickBoot header did not contain a sync word, the FPGAconfiguration logic continues searching through the flash and finds the syncword in this golden bitstream. Thus, configuration can start here.The "golden" image contains:1. A standard bitstream, which is the "golden" design.2. Dummy pad words (0xFFFFFFFF) to fill the area b

The QuickBoot flash memory components are similar to the MultiBoot flash memory components, except that the MultiBoot warm boot jump sequence is a separate component from the golden bitstream component. The subcomp