What’s New in MIPI I3C Basicand the I3C Ecosystem15 September 2021Tim McKeeMatthew SchnoorMichele ScarlatellaIntel Corporation,MIPI I3C WorkingGroup ChairIntel Corporation,MIPI I3C HCISubgroup LeadI3C Technical ConsultantMIPI Alliance1 2021 MIPI Alliance, Inc.
Webinar Agenda1. What’s new with I3C/I3C Basic–Tim McKee - MIPI I3C Working Group Chair2. What’s new with the MIPI I3C Host Controller Interface (HCI)–Matthew Schnoor - MIPI I3C HCI Subgroup Lead3. How I3C Enables Power Efficient Designs– Michele Scarlatella - I3C Technical Consultant4. Questions and Answers2 2021 MIPI Alliance, Inc.
What’s new with I3C/I3C BasicTim McKeeIntel Corporation,MIPI I3C Working Group Chair3 2021 MIPI Alliance, Inc.
MIPI I3C Interface - IntroductionFast Growing Sensor MarketsMobileConsumerWearablesIoTIndustrial IoTSmarter, more capableAvg 20 sensors/device(projected) AccelerometerGyroscopeMagnetometerAmbient lightPressureAutomotiveTransportationI3C - a scalable, cost-effectiveinterfaceHumidityTemperature. others Targeting mobile & IoT devices,automotive, server manageabilitySimplify connecting and managingmultiple sensors in a deviceReduced pin count and signal pathsSupport for low-power, high-speedcommunication (vs. I2C/SPI/UART)Multi-host arbitrationLow complexity ( 2Kgates / target)Compatibility with I2C devices4 2021 MIPI Alliance, Inc.
Evolution of MIPI I3C Interface SpecificationI3C v1.0I3C v1.1I3C v1.1.1 First versionspecification Released Dec 2016 New I3C specification New features added Released Nov 2019 Updated with errataI3C Basic v1.0 License free Subset of features Released Jul 2018 No new major features Released Jun 2021I3C Basic v1.1.1 More closelyaligned feature set Released Jul 20215 2021 MIPI Alliance, Inc.5
MIPI I3C Key FeaturesFast Efficient Communication Channel Multidrop SDA/SCL 2-wire interface Dynamic switch between pull-up/push-pull/Hi-ZLine Coding modes for higher throughput: 12.5 MHz max Clock rate1.2V-3.3V Voltage supportedSDR, HDR-DDR/TSP/TSL/BTMultilane x2, x4System Management Low EMIPhysical layer CMOS I/O compatibleAdvanced Functions Multi-operation via repeated STARTUnicast, Broadcast, Multicast messagesIn-Band Interrupt with qualified informationDevice resetHot-JoinError detection (parity, CRC)From v1.1Primary & Secondary ControllersDynamic Address Assignmentincluding Group AddressingDevice Code Assignment (by MIPI)Descriptors: DCR Device Configuration Register BCR Bus Configuration RegisterBackward Compatibility Mixed-bus operation: I3C and I2C devices Static address space reserved for I2C legacydevicesFast operations invisible to I2C thanks to50ns spike filter6 2021 MIPI Alliance, Inc.
New Specifications for 2021 I3C Version 1.1.1– Clarifications (Small errors and typos)– Terminology changes (Controller/Target)– Incorporation of previous modifications (Target Reset) I3C Basic Version 1.1.1– Synchronized with I3C v1.1.1– Clarifications and Terminology changes– New features (HDR Modes, CCCs, Timing Control) I3C Host Controller Interface (HCI) Version 1.1– Presentation coming up .7 2021 MIPI Alliance, Inc.
Where is I3C Being Leveraged? JEDEC– Serial Presence Detect (SPD) Hub for DDR Memory DMTF– Management Component Transport Protocol (MCTP) andI3C protocols for bus management Others in development–––––PCIe I3C sidebandI3C over IEEE 1722Protocol Adaptation Layer (PAL) for I3C over A-PHYETSI for Smart Secure PlatformMore?8 2021 MIPI Alliance, Inc.
MIPI I3C Ecosystem / Support Conformance Test Suite (CTS) Host Controller Interface I3C Subsystem Linux Kernel r-api/i3c/index.html Debug for I3C: Enables debugging over I3C DisCo for I3C: Simplifies software integration FAQs Plugfest Interoperability Testing Application Notes9 2021 MIPI Alliance, Inc.
Get Involved / Sources of Further Information I3C Working Group– Open to MIPI contributor members (Meets: Wednesdays 8am PST) Contact the Working Group– Let us know your questions/comments– Email: [email protected] (members)– Email: [email protected] (non-members) I3C Supporting Documents– FAQs– App Notes– Errata Website: cification10 2021 MIPI Alliance, Inc.
What’s new with the MIPI I3CHost Controller Interface (HCI)Matthew SchnoorIntel Corporation,MIPI I3C HCI Subgroup Lead11 2021 MIPI Alliance, Inc.
I3C Host Controller Interface (HCI) – What and Why? Intended to standardize the interface that platform software uses to access I3CTarget Devices and their capabilities.Enables a rich ecosystem for development; usable for various use cases,including IoT, mobile, datacenter and other emerging applications.Example of I3C Bus with connection to Host via System BusI3C HCI Specification provides a standardized command/response interface12 2021 MIPI Alliance, Inc.
Benefits of standardizing the interface Ecosystem can use a common softwaredriver to detect, configure and present I3CTargets to their application– Common register definitions for Controllerconfiguration– Common data structures for transfercommands and I3C Target responses– Two operating modes allow implementerflexibility for different needs Application developers can focus theirattention on higher-level flowsImplementers can define ExtendedCapabilities as needed (per use case)Example of I3C HCI ImplementationI3C HCI Specification defines the common register definitions,data structures and operating modes for the implementer.13 2021 MIPI Alliance, Inc.
History of I3C HCI Version 1.0 – Adopted 4 April 2018–––––––Supports up to 32 I2C and I3C Target Devices per I3C BusSupports features defined in I3C v1.0 and (subsequent) I3C Basic v1.0Supports I3C Transfers in SDR Mode, HDR-DDR and HDR-Ternary ModesSupports Broadcast and Direct CCCs (with managed framing)Supports Time Stamping (Asynchronous)Supports Dynamic Address Assignment with ENTDAA and SETDASA CCCsOperating modes: PIO Mode (lightweight HW, Host-intensive for each TX/RX transfer) DMA Mode (adds memory controller, offloads TX/RX queue operations from Host)14 2021 MIPI Alliance, Inc.
History of I3C HCI Version 1.1 – Adopted 20 May 2021–––––––––Supports many of the features defined in I3C v1.1/v1.1.1 and (subsequent) I3C Basic v1.1.1Adds support for Grouped AddressingAdds Dynamic Address Assignment method for SETAASA (as Broadcast CCC)Adds support for CCCs with Defining BytesAdds support for Target Reset Pattern flows (with optional preceding RSTACT CCCs)Adds more robust error handling methods and Bus reset/recovery flowsAdds scatter-gather support (optional) for DMA ModeMany clarifications, bug fixes and other issues addressed (from implementer feedback)Expanded and reorganized “Theory of Operation” section15 2021 MIPI Alliance, Inc.
I3C HCI enables the I3C ecosystem Linux I3C HCI Driver has been released to the open-source community––– Useful as a key component of integrations and other I3C subsystems– Driver development funded by MIPI AllianceAvailable in mainstream Linux kernel tree (v5.x)Supports HCI v1.1 (adopted) and 2.0 (early draft)HCI-compliant I3C Controller IPs are available on the market todayMIPI Software WG wants to hear about your use integrations cases, featurerequests or any improvement ideas 16 2021 MIPI Alliance, Inc.
Next Steps for I3C HCI Version 1.2 – optional normative feature adds, development is in progress–––––– Answering requests from other MIPI WGs, MIPI Contributors and industry liaisons, including:Support for I3C “Dead Bus Recovery” methods (optional)Better support for CSI-2 v4.0 use cases based on I3COptional support for Standby mode in limited Secondary Controller RoleOptional support for scheduled commands (i.e., periodic polling of I3C Targets)Support for HDR Flow Control capabilities, etc.WG aims to preserve SW compatibility and wisely invest effort in HCI v1.x, to addsupport for new I3C optional capabilities that address specific use cases.17 2021 MIPI Alliance, Inc.
Next Steps for I3C HCI Version 2.0 – generational advancement; feature development currently paused–––––– Looking to add performance and capability upgrades requested by MIPI Contributors, including:Support for additional HDR Modes (e.g., HDR-BT)Support for Multi-Lane transfersAdditional support for I3C Secondary Controller roleAdditional run-time controls for Queue/Ring statusMore extensibility and configurabilityLarger feature additions will require substantial changes to HCI definitions, withimpact to the existing ecosystem we need MIPI Contributors to review andcomment.18 2021 MIPI Alliance, Inc.
How I3C Enables Power Efficient DesignsMichele ScarlatellaI3C Technical Consultant,MIPI Alliance19 2021 MIPI Alliance, Inc.
How I3C helps Power Efficiency for IoT Devices Many classes of IoT devices work under tight power budget(Wearables, in-file data collection units, etc.)Low energy consumption and Power efficiency are key features––– Low-voltage operationRunning on batteryNon-rechargeable, targeting several years operationI3C can help solve above challenges Excellent bus electrical characteristicsHandling of synchronous and asynchronous eventsSelective power management of sub-componentsSystem segmentationI3C Features & specs are great help to System Designers toarchitect Power Efficient IoT Devices for their next project20 2021 MIPI Alliance, Inc.
Parameters Affecting Energy rDebugInterfaceI3C BusInertialSensorTempSensorTouchSensor Low voltage operationBus electrical characteristicsVoltage compatibilityEfficiency of bus transactions– Scheduled and asynchronous dataacquisition and transfer Selective power managementof sub-unitsManaging «idle time»21 2021 MIPI Alliance, Inc.
I3C Bus Electrical Features (1/2) ElectricalVDD– Low Operating voltage: 3.3V - 1.2V( soon below)– Bus capacitance 10pF / device (total 50-100pF)– Pull-up: 1.1-2.8 kΩ Pull-up (2.83KΩ @ 3.3V)Factors affecting Energy consumption– Switching shoot-through currentØ optimize IP selectionBus capacitancePad capacitance– Bus capacitanceØ keep short bus length,Ø reduced Capacitance on input padsVDD– Pull-down currentØ minimize pull-down timeØ use push-pull whenever possible22 2021 MIPI Alliance, Inc.
I3C Bus Electrical Features (2/2) When not active, I3C bus lines can be in three states:––– Pull-up (Open Drain)High-ZHigh-Keeper (light pull-up, higher dynamic R)SCL is (almost) always Push-Pull–Pull-upHigh-ZNo clock stretching allowedSDA is switched dynamically by Active Controllerbetween Pull-up (Open Drain), Push-Pull, High-Z,High-KeeperHighKeeper23 2021 MIPI Alliance, Inc.
Typical Bus TransactionHighlights: Line interfaces structured toavoid inefficient pull-upmode High Data Rate (HDR) modesboast excellent mJ/bitperformance Faster bus transactions implyreduced CPU cyclesSCL is usually in power efficient Push/Pullmode, driven by Controller(**)(*) If assigned Dynamic Addresses values are 0x3F (54 avail.)(**) There are a few instances where SCL is in Open drain mode,mostly related to I2C compatibility24 2021 MIPI Alliance, Inc.
I3C Energy Consumption Estimate1/8th lower than I2C High Data Rate (HDR):– Switching waveforms preserve goodpower performance for all modes Faster transaction execution Reduced CPU cyclesSDR Single Data RateDDR Double Data RateTSL Ternary Symbol Legacy inclusive busTSP Ternary Symbol Pure bus25 2021 MIPI Alliance, Inc.
Optimize by Bus SegmentationMinimize Cbus with fewer devices in the busVDDHost ProcessorPrimaryControllerMixed mode I3C/I2CMinimize tlow avoiding I2C devices Isolate I3C high activity devices Consider Segmentation usingRouting Devices– Low activity bus & mixed mode I3C/I2C– High activity bus (pure I3C) Better processing efficiencyLegacy I2CDeviceI2C SerialEEPROMRoutingDevice Pure I3CMCUSecondaryControllerGyroIMU Specs ref. v1.1.1 (18.104.22.168.17/20)26 2021 MIPI Alliance, Inc.
Improving Idle-time with Bus ConditionsInforming Targets of bus idle condition facilitates low power management Specific CCCs allocated: ENTAS[0.3] ENTASx CCC informs Target(s) about lowActivity state CCCBusIdle timeactivity intervals– 2 ms & 50 ms idle time can rack upsignificant power savingsRemarks: ENTASx CCC is only a “suggestion” to TargetThis does not replace applicationspecific or custom power savingsagreements (i.e., “private contracts”)ENTAS01 μsENTAS1100 μsENTAS22 msENTAS350 ms27 2021 MIPI Alliance, Inc.
Efficient Data Acquisition with In-Band-Interrupts (IBI)IBI allows fast and efficient asynchronous data acquisition, and event processing Data produced by a target is promptly transferred to upstream controller for further processingIBI are intended as an efficient mechanism for Targets to grab Controller attentionAvoids extra dedicated wires, or inefficient polling mechanismAsynchronous EventSend datawith IBIDataAcquisitionData available atMCU for ProcessingFurtheractionstimeFew µsec28 2021 MIPI Alliance, Inc.
Efficient Data Acquisition with IBIHow is it done:Additional data is inserted aspart of the IBI requestAdditional data size definitionby SETMRL CCC Data transfer by a READ or usingMandatory Data Byte (MDB)– Active if BCR 1 Structure of MDB:– Interrupt Group Identifier (3-bits)– Specific Interrupt Identifier (4 bits)– Vendor defined meaning possibleSpecs ref. v1.1.1 (5.1.6, 22.214.171.124.6)29 2021 MIPI Alliance, Inc.
Power Management with Hot-Join (HJ)HJ Primary usesMCU1. Wake-up signalPrimaryController Attach device after bus is configuredProvision exist for late power-up of atargetImproved power management2. Hot-Join reqI3C BusSensorSensor SensorCommUnit Selective powering of sub-unitsWake-up only when neededWake-up signal can be– Out-of-band (HW wire)– In-band with Target Reset Action(RSTACT) target reacting to apredefined pattern(*) IBI In Band Interrupt30 2021 MIPI Alliance, Inc.
Power management with Hot-Join - How HJ has similar pattern to IBI with predefined high-priority address 0x02 Dynamic Address Assignment need to be executed During off-state target must insure no power is inadvertently drained through SDA/SCL wires31 2021 MIPI Alliance, Inc.
Summary and Key Takeaways I3C electrical characteristics are well suited for IoT low-power deviceswith wide voltage classes & low power consumptionI3C is not just a ‘bit-pipe’ but modern bus with many high-level functionsthat facilitate the design of power efficient IoT devices– Segmentation into sub-systems– Improved event management– Efficient data acquisition Hot Join feature allow ‘power segmented’ designs, by keeping unitsactive only when needed, with interoperable and standard proceduresAs more and more I3C MCU’s and sensors are expected to be in themarket, I3C is a key candidate for next generation designs32 2021 MIPI Alliance, Inc.
MIPI I3C Additional Information #1 MIPI I3C Basic Specification -download MIPI I3C Specification ensor-specification MIPI I3C v1.1 – A Conversation with Ken 1.1-a-conversation-with-ken-foust Whitepaper: Introduction to the MIPI I3C Standardized Sensor Interface–https://resources.mipi.org/hubfs/MIPI Alliance I3C Whitepaper.pdf MIPI DevCon 2021 – I3C related sessions:–MIPI I3C Signal Integrity Challenges on DDR5-based Server Platform Solutions –MIPI I3C Application and Validation Models for IoT Sensor Nodes ot-sensor-nodesMIPI I3C Under the Spotlight: A Fireside Chat with the I3C Experts nder-spotlight-fireside-chat-i3c-experts33 2021 MIPI Alliance, Inc.
MIPI I3C Additional Information #2 I3C Basic in JEDEC DDR5: A Sum Greater Than Its asic-in-jedec-ddr5-a-sum-greater-than-its-parts System Integrators Application Note for MIPI I3C v1.0 and I3C Basic v1.0 mipi I3C-and-I3C-Basic app-note-system-integrator v1-0p.pdf I3C and I3C Basic Frequently Asked Questions f I3C Application Note: Hot-Join pers/mipi I3C app-note Hot-Join v1-0p.pdf I3C Application Note: Virtual Devices and Virtual Targets pers/mipi I3C app-note Virtual-Devices v1-0p.pdf I3C Basic Target Reset (now in c-download I3C Host Controller c-hci34 2021 MIPI Alliance, Inc.
Questions and Answers35 2021 MIPI Alliance, Inc.
Thanks for attending!36 2021 MIPI Alliance, Inc.
Sep 15, 2021 · – Low-voltage operation – Running on battery – Non-rechargeable, targeting several years operation I3C can help solve above challenges Excellent bus electrical characteristics Handling of synchronous and asynchronous events Selective