Transcription

ESP32Technical Reference ManualVersion 4.6Espressif SystemsCopyright 2021www.espressif.com

About This ManualThe ESP32 Technical Reference Manual is addressed to application developers. The manual provides detailedand complete information on how to use the ESP32 memory and peripherals.For pin definition, electrical characteristics, and package information, please see ESP32 Datasheet.Document UpdatesPlease always refer to the latest version at ments.Revision HistoryFor any changes to this document over time, please refer to the last page.Documentation Change NotificationEspressif provides email notifications to keep customers updated on changes to technical documentation. Pleasesubscribe at ad certificates for Espressif products from www.espressif.com/en/certificates.

ContentsContents1System and l Description261.3.1Address Mapping261.3.2Embedded Memory261.3.2.1Internal ROM 0271.3.2.2Internal ROM 1271.3.2.3Internal SRAM 0271.3.2.4Internal SRAM 1281.3.2.5Internal SRAM 2281.3.2.6DMA291.3.2.7RTC FAST Memory291.3.2.8RTC SLOW Memory291.3.3External etric PID Controller Peripheral321.3.5.2Non-Contiguous Peripheral Memory Ranges321.3.5.3Memory Speed332Interrupt Matrix al Description342.3.1Peripheral Interrupt Source342.3.2CPU Interrupt372.3.3Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU372.3.4CPU NMI Interrupt Mask382.3.5Query Current Interrupt Status of Peripheral Interrupt Source382.4Registers383Reset and Clock393.1System Reset393.1.1Introduction393.1.2Reset Source393.2System Clock403.2.1Introduction403.2.2Clock Source403.2.3CPU Clock413.2.4Peripheral Clock423.2.4.142Espressif SystemsAPB CLK Source3Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents3.2.4.2REF TICK Source423.2.4.3LEDC SCLK Source433.2.4.4APLL SCLK Source433.2.4.5PLL D2 CLK Source433.2.4.6Clock Source Considerations433.2.5Wi-Fi BT Clock433.2.6RTC Clock433.2.7Audio PLL444IO MUX and GPIO Matrix (GPIO, IO MUX)454.1Overview454.2Peripheral Input via GPIO Matrix464.2.1Summary464.2.2Functional Description464.2.3Simple GPIO Input47Peripheral Output via GPIO Matrix474.3.1Summary474.3.2Functional Description484.3.3Simple GPIO Output494.34.44.5Direct I/O via IO MUX494.4.1Summary494.4.2Functional Description49RTC IO MUX for Low Power and Analog I/O494.5.1Summary494.5.2Functional Description494.6Light-sleep Mode Pin Functions504.7Pad Hold Feature504.8I/O Pad Power Supplies504.8.1524.9Peripheral Signal List524.10IO MUX Pad List574.11RTC MUX Pin List584.12Register Summary584.12.1 GPIO Matrix Register Summary584.12.2 IO MUX Register Summary604.12.3 RTC IO MUX Register Summary61Registers624.13.1 GPIO Matrix Registers624.13.2 IO MUX Registers714.13.3 RTC IO MUX Registers735DPort onal Description875.3.1874.13VDD SDIO Power DomainSystem and Memory RegisterEspressif Systems4Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents5.3.2Reset and Clock Registers875.3.3Interrupt Matrix Register875.3.4DMA Registers875.3.5MPU/MMU Registers875.3.6APP CPU Controller Registers885.3.7Peripheral Clock Gating and Reset885.4Register Summary895.5Registers966DMA Controller (DMA)1126.1Overview1126.2Features1126.3Functional Description1126.3.1DMA Engine Architecture1126.3.2Linked List1136.4UART DMA (UDMA)1136.5SPI DMA Interface1156.6I2S DMA Interface1167SPI Controller (SPI)1177.1Overview1177.2SPI Features1187.3GP-SPI1187.47.57.67.3.1GP-SPI Four-line Full-duplex Communication1197.3.2GP-SPI Four-line Half-duplex Communication1197.3.3GP-SPI Three-line Half-duplex Communication1207.3.4GP-SPI Data Buffer120GP-SPI Clock Control1217.4.1GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA)1217.4.2GP-SPI Timing122Parallel QSPI1237.5.1123Communication Format of Parallel QSPIGP-SPI Interrupt Hardware1247.6.1SPI Interrupts1247.6.2DMA Interrupts1247.7Register Summary1257.8Registers1288SDIO Slave onal Description1518.3.1SDIO Slave Block Diagram1518.3.2Sending and Receiving Data on SDIO Bus1528.3.3Register Access1528.3.4DMA152Espressif Systems5Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents8.3.5Packet-Sending/-Receiving Procedure1538.3.5.1Sending Packets to SDIO Host1548.3.5.2Receiving Packets from SDIO Host1558.3.6SDIO Bus Timing1568.3.7Interrupt1578.3.7.1Host Interrupt1578.3.7.2Slave Interrupt1578.4Register Summary1588.5SLC Registers1608.6SLC Host Registers1688.7HINF Registers1829SD/MMC Host Controller1839.1Overview1839.2Features1839.3SD/MMC External Interface Signals1839.4Functional Description1849.4.1SD/MMC Host Controller and Path1859.4.3Data Path1869.4.3.1Data Transmit Operation1869.4.3.2Data Receive Operation1879.5Software Restrictions for Proper CIU Operation1879.6RAM for Receiving and Sending Data1889.6.1Transmit RAM Module1889.6.2Receive RAM Module1889.7Descriptor Chain1899.8The Structure of a Linked List1899.9Initialization1919.9.1DMAC Initialization1919.9.2DMAC Transmission Initialization1919.9.3DMAC Reception Initialization1929.10Clock Phase Selection1939.11Interrupt1939.12Register Summary1939.13Registers19510 Ethernet Media Access Controller (MAC)21310.1Overview21310.2EMAC CORE21510.2.1 Transmit Operation21510.2.1.1 Transmit Flow Control21610.2.1.2 Retransmission During a Collision21610.2.2 Receive OperationEspressif Systems2166Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents10.2.2.1 Reception Protocol21710.2.2.2 Receive Frame Controller21710.2.2.3 Receive Flow Control21710.2.2.4 Reception of Multiple Frames21810.2.2.5 Error Handling21810.2.2.6 Receive Status Word21810.3MAC Interrupt Controller21810.4MAC Address Filtering21910.4.1 Unicast Destination Address Filtering21910.4.2 Multicast Destination Address Filtering21910.4.3 Broadcast Address Filtering21910.4.4 Unicast Source Address Filtering21910.4.5 Inverse Filtering Operation21910.4.6 Good Transmitted Frames and Received Frames22110.5EMAC MTL (MAC Transaction Layer)22110.6PHY Interface22110.6.1 MII (Media Independent Interface)22210.6.1.1 Interface Signals Between MII and PHY22210.6.1.2 MII Clock22310.6.2 RMII (Reduced Media-Independent Interface)22310.6.2.1 RMII Interface Signal Description22410.6.2.2 RMII Clock22410.6.3 Station Management Agent (SMA) Interface22510.6.4 RMII Timing22510.7Ethernet DMA Features22610.8Linked List Descriptors22610.8.1 Transmit Descriptors22610.8.2 Receive Descriptors232Register Summary23710.910.10 Registers24011 I2C Controller al Description27811.3.1 Introduction27811.3.2 Architecture27911.3.3 I2C Bus Timing28011.3.4 I2C cmd Structure28111.3.5 I2C Master Writes to Slave28211.3.6 Master Reads from Slave28611.3.7 Interrupts28811.4Register Summary28911.5Registers29112 I2S Controller (I2S)Espressif Systems3027Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents12.1Overview30212.2Features30312.3The Clock of I2S Module30412.4I2S Mode30512.4.1 Supported Audio Standards30512.4.1.1 Philips Standard30512.4.1.2 MSB Alignment Standard30512.4.1.3 PCM Standard30612.4.2 Module Reset30612.4.3 FIFO Operation30612.4.4 Sending Data30712.4.5 Receiving Data30812.4.6 I2S Master/Slave Mode31012.4.7 I2S PDM310Camera-LCD Controller31212.5.1 LCD Master Transmitting Mode31212.5.2 Camera Slave Receiving Mode31312.5.3 ADC/DAC mode314I2S Interrupts31512.6.1 FIFO Interrupts31512.6.2 DMA Interrupts31512.7Register Summary31512.8Registers31812.512.613 UART Controller (UART)33613.1Overview33613.2UART Features33613.3Functional Description33613.3.1 Introduction33613.3.2 UART Architecture33713.3.3 UART RAM33813.3.4 Baud Rate Detection33913.3.5 UART Data Frame33913.3.6 Flow Control34013.413.513.3.6.1 Hardware Flow Control34013.3.6.2 Software Flow Control34113.3.7 UART DMA34113.3.8 UART Interrupts34113.3.9 UHCI Interrupts342Register Summary34313.4.1 UART Registers34313.4.2 UHCI Registers344Registers34614 LED PWM Controller (LEDC)37814.1378IntroductionEspressif Systems8Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents14.2Functional Description37814.2.1 Architecture37814.2.2 Timers37914.2.3 Channels38014.2.4 Interrupts38114.3Register Summary38114.4Registers38415 Remote Control Peripheral (RMT)39415.1Introduction39415.2Functional Description39415.2.1 RMT Architecture39415.2.2 RMT RAM39515.2.3 Clock39515.2.4 Transmitter39515.2.5 Receiver39615.2.6 Interrupts39615.3Register Summary39615.4Registers39716 Motor Control PWM odules40516.3.1 Overview40516.3.1.1 Prescaler Submodule40516.3.1.2 Timer Submodule40516.3.1.3 Operator Submodule40616.3.1.4 Fault Detection Submodule40816.3.1.5 Capture Submodule40816.3.2 PWM Timer Submodule40816.3.2.1 Configurations of the PWM Timer Submodule40816.3.2.2 PWM Timer’s Working Modes and Timing Event Generation40916.3.2.3 PWM Timer Shadow Register41316.3.2.4 PWM Timer Synchronization and Phase Locking41316.3.3 PWM Operator Submodule41316.3.3.1 PWM Generator Submodule41516.3.3.2 Dead Time Generator Submodule42516.3.3.3 PWM Carrier Submodule43016.3.3.4 Fault Handler Submodule43316.3.4 Capture Submodule43416.3.4.1 Introduction43416.3.4.2 Capture Timer43516.3.4.3 Capture Channel43516.4Register Summary43616.5Registers438Espressif Systems9Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents17 Pulse Count Controller (PCNT)48517.1Overview48517.2Functional Description48517.2.1 Architecture48517.2.2 Counter Channel Inputs48617.2.3 Watchpoints48617.2.4 Examples48717.2.5 Interrupts48717.3Register Summary48717.4Registers48918 Timer Group (TIMG)49418.1Introduction49418.2Functional Description49418.2.1 16-bit Prescaler49418.2.2 64-bit Time-base Counter49418.2.3 Alarm Generation49518.2.4 MWDT49518.2.5 Interrupts49518.3Register Summary49518.4Registers49719 Watchdog Timers tional Description50519.3.1 Clock50519.3.1.1 Operating Procedure50519.3.1.2 Write Protection50619.3.1.3 Flash Boot Protection50619.3.1.4 Registers50620 eFuse 3Functional Description50720.3.1 Structure50720.420.3.1.1 System Parameter efuse wr disable50920.3.1.2 System Parameter efuse rd disable50920.3.1.3 System Parameter coding scheme50920.3.1.4 BLK3 part reserve51020.3.2 Programming of System Parameters51120.3.3 Software Reading of System Parameters51320.3.4 The Use of System Parameters by Hardware Modules51520.3.5 Interrupts515Register Summary515Espressif Systems10Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents20.5Registers51821 Two wire Automotive Interface nal Protocol52921.3.1 TWAI Properties52921.3.2 TWAI Messages53021.3.2.1 Data Frames and Remote Frames53121.3.2.2 Error and Overload Frames53321.3.2.3 Interframe Space53421.3.3 TWAI Errors53521.3.3.1 Error Types53521.3.3.2 Error States53521.3.3.3 Error Counters53621.3.4 TWAI Bit Timing21.421.553721.3.4.1 Nominal Bit53721.3.4.2 Hard Synchronization and Resynchronization538Architectural Overview53821.4.1 Registers Block53821.4.2 Bit Stream Processor54021.4.3 Error Management Logic54021.4.4 Bit Timing Logic54021.4.5 Acceptance Filter54021.4.6 Receive FIFO540Functional Description54021.5.1 Modes54121.5.1.1 Reset Mode54121.5.1.2 Operation Mode54121.5.2 Bit Timing54121.5.3 Interrupt Management54221.5.3.1 Receive Interrupt (RXI)54221.5.3.2 Transmit Interrupt (TXI)54321.5.3.3 Error Warning Interrupt (EWI)54321.5.3.4 Data Overrun Interrupt (DOI)54321.5.3.5 Error Passive Interrupt (TXI)54421.5.3.6 Arbitration Lost Interrupt (ALI)54421.5.3.7 Bus Error Interrupt (BEI)54421.5.4 Transmit and Receive Buffers54421.5.4.1 Overview of Buffers54421.5.4.2 Frame Information54521.5.4.3 Frame Identifier54521.5.4.4 Frame Data54621.5.5 Receive FIFO and Data Overruns54621.5.6 Acceptance Filter54721.5.6.1 Single Filter ModeEspressif Systems54711Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents21.5.6.2 Dual FIlter Mode54821.5.7 Error Management54821.5.7.1 Error Warning Limit54921.5.7.2 Error Passive55021.5.7.3 Bus-Off and Bus-Off Recovery55021.5.8 Error Code Capture55121.5.9 Arbitration Lost Capture55221.6Register Summary55221.7Registers55422 AES Accelerator tional Description56722.3.1 AES Algorithm Operations56722.3.2 Key, Plaintext and Ciphertext56722.3.3 Endianness56722.3.4 Encryption and Decryption Operations57022.3.5 Speed57022.4Register Summary57022.5Registers57123 SHA Accelerator tional Description57323.3.1 Padding and Parsing the Message57323.3.2 Message Digest57323.3.3 Hash Operation57323.3.4 Speed57423.4Register Summary57423.5Registers57624 RSA Accelerator tional Description58224.3.1 Initialization58224.3.2 Large Number Modular Exponentiation58224.3.3 Large Number Modular Multiplication58424.3.4 Large Number Multiplication58424.4Register Summary58524.5Registers58625 Random Number Generator (RNG)58825.1588IntroductionEspressif Systems12Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents25.2Feature58825.3Functional Description58825.4Programming Procedure58925.5Register Summary58925.6Register58926 External Memory Encryption and Decryption onal Description59026.3.1 Key Generator59126.3.2 Flash Encryption Block59126.3.3 Flash Decryption Block59226.4Register Summary59226.5Register59427 Memory Management and Protection Units (MMU, ional Description59527.3.1 PID Controller59527.3.2 MPU/MMU59527.3.2.1 Embedded Memory59627.3.2.2 External Memory60227.3.2.3 Peripheral60828 Process ID Controller al Description61028.3.1 Interrupt Identification61028.3.2 Information Recording61128.3.3 Proactive Process Switching61228.4Register Summary61428.5Registers61529 On Chip Sensors and Analog Signal Processing61929.1Introduction61929.2Capacitive Touch Sensor61929.2.1 Introduction61929.2.2 Features61929.2.3 Available GPIOs62029.2.4 Functional Description62029.2.5 Touch FSM621SAR ADC62129.3.1 Introduction62129.3Espressif Systems13Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents29.429.529.629.729.3.2 Features62229.3.3 Outline of Function62329.3.4 RTC SAR ADC Controllers62429.3.5 DIG SAR ADC Controllers625Hall Sensor62729.4.1 Introduction62729.4.2 Features62729.4.3 Functional Description627DAC62829.5.1 Introduction62829.5.2 Features62829.5.3 Structure62929.5.4 Cosine Waveform Generator62929.5.5 DMA support630Register Summary63129.6.1 Sensors63129.6.2 Advanced Peripheral Bus63129.6.3 RTC I/O632Registers63329.7.1 Sensors63329.7.2 Advanced Peripheral Bus64329.7.3 RTC I/O64630 ULP Coprocessor tional Description64830.4Instruction Set64830.4.1 ALU - Perform Arithmetic/Logic Operations64830.530.4.1.1 Operations Among Registers64930.4.1.2 Operations with Immediate Value65030.4.1.3 Operations with Stage Count Register65030.4.2 ST – Store Data in Memory65130.4.3 LD – Load Data from Memory65130.4.4 JUMP – Jump to an Absolute Address65230.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0)65230.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count Register)65330.4.7 HALT – End the Program65330.4.8 WAKE – Wake up the Chip65430.4.9 Sleep – Set the ULP Timer’s Wake-up Period65430.4.10 WAIT – Wait for a Number of Cycles65430.4.11 ADC – Take Measurement with ADC65530.4.12 I2C RD/I2C WR – Read/Write I²C65530.4.13 REG RD – Read from Peripheral Register65630.4.14 REG WR – Write to Peripheral Register657ULP Program Execution657Espressif Systems14Submit Documentation FeedbackESP32 TRM (Version 4.6)

Contents30.630.730.8RTC I2C Controller65930.6.1 Configuring RTC I2C65930.6.2 Using RTC I2C66030.6.2.1 I2C RD - Read a Single Byte66030.6.2.2 I2C WR - Write a Single Byte66030.6.2.3 Detecting Error Conditions66130.6.2.4 Connecting I²C Signals661Register Summary66130.7.1 SENS ULP Address Space66130.7.2 RTC I2C Address Space662Registers66330.8.1 SENS ULP Address Space66330.8.2 RTC I2C Address Space66531 Low Power Management (RTC tional Description67131.3.1 Overview67231.3.2 Digital Core Voltage Regulator67231.3.3 Low-Power Voltage Regulator67231.3.4 Flash Voltage Regulator67331.3.5 Brownout Detector67431.3.6 RTC Module67431.3.7 Low-Power Clocks67631.3.8 Power-Gating Implementation67731.3.9 Predefined Power Modes67831.3.10 Wakeup Source67931.3.11 RTC Timer68031.3.12 RTC Boot68031.4Register Summary68131.5Registers684Glossary710Abbreviations for Peripherals710Abbreviations for Registers710Revision History711Espressif Systems15Submit Documentation FeedbackESP32 TRM (Version 4.6)

List of TablesList of Tables1Address Mapping262Embedded Memory Address Mapping273Module with DMA294External Memory Address Mapping295Cache memory mode306Peripheral Address Mapping317PRO CPU, APP CPU Interrupt Configuration358CPU Interrupts379PRO CPU and APP CPU Reset Reason Values3910CPU CLK Source4111CPU CLK Derivation4112Peripheral Clock Usage4213APB CLK Derivation4214REF TICK Derivation4315LEDC SCLK Derivation4316IO MUX Light-sleep Pin Function Registers5017GPIO Matrix Peripheral Signals5218IO MUX Pad Summary5719RTC MUX Pin Summary5825Mapping Between SPI Bus Signals and Pin Function Signals11726Command Definitions Supported by GP-SPI Slave in Half-duplex Mode11927Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master12128Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave12133SD/MMC Signal 39Destination Address Filtering22040Source Address Filtering22041Timing Parameters - Receiving Data22542Timing Parameters – Transmitting Data22643Transmit Descriptor 0 (TDES0)22744Transmit Descriptor 1 (TDES1)23145Transmit Descriptor 2 (TDES2)23146Transmit Descriptor 3 (TDES3)23147Transmit Descriptor 6 (TDES6)23148Transmit Descriptor 7 (TDES7)23249Receive Descriptor 0 (RDES0)23250Receive Descriptor 1 (RDES1)23551Receive Descriptor 2 (RDES2)23552Receive Descriptor 3 (RDES3)23553Receive Descriptor 4 (RDES4)236Espressif Systems16Submit Documentation FeedbackESP32 TRM (Version 4.6)

List of Tables54Receive Descriptor 6 (RDES6)23755Receive Descriptor 7 (RDES7)23757SCL Frequency Configuration28059I2S Signal Bus Description30360Register Configuration30761Send Channel Mode30762Modes of Writing Received Data into FIFO and the Corresponding Register Configuration30963The Register Configuration to Which the Four Modes Correspond30964Upsampling Rate Configuration31165Down-sampling Configuration31269Commonly-used Frequencies and Resolutions37972Configuration Parameters of the Operator Submodule40773Timing Events Used in PWM Generator41574Timing Events Priority When PWM Timer Increments41675Timing Events Priority when PWM Timer Decrements41676Dead Time Generator Switches Control Registers42677Typical Dead Time Generator Operating Modes42782System Parameters50783BLOCK1/2/3 Encoding51084Program Registers51185Timing Configuration51386Software Read Registers51488Data Frames and Remote Frames in SFF and EFF53289Error Frame53390Overload Frame53491Interframe Space53492Segments of a Nominal Bit Time53793Bit Information of TWAI CLOCK DIVIDER REG; TWAI Address 0x1854194Bit Information of TWAI BUS TIMING 1 REG; TWAI Address 0x1c54295Buffer Layout for Standard Frame Format and Extended Frame Format54496TX/RX Frame Information (SFF/EFF) TWAI Address 0x4054597TX/RX Identifier 1 (SFF); TWAI Address 0x4454598TX/RX Identifier 2 (SFF); TWAI Address 0x4854699TX/RX Identifier 1 (EFF); TWAI Address 0x44546100TX/RX Identifier 2 (EFF); TWAI Address 0x48546101TX/RX Identifier 3 (EFF); TWAI Address 0x4c546102TX/RX Identifier 4 (EFF); TWAI Address 0x50546103Bit Information of TWAI ERR CODE CAP REG; TWAI Address 0x30551104Bit Information of Bits SEG.4 - SEG.0551105Bit Information of TWAI ARB LOST CAP REG; TWAI Address 0x2c552107Operation Mode567108AES Text Endianness568109AES-128 Key Endianness569110AES-192 Key Endianness569111AES-256 Key Endianness569117MPU and MMU Structure for Internal Memory596Espressif Systems17Submit Documentation FeedbackESP32 TRM (Version 4.6)

List of Tables118MPU for RTC FAST Memory597119MPU for RTC SLOW Memory597120Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2598121Page Boundaries for SRAM0 MMU599122Page Boundaries for SRAM2 MMU599123DPORT DMMU TABLEn REG & DPORT IMMU TABLEn REG600124MPU for DMA601125Virtual Address for External Memory603126MMU Entry Numbers for PRO CPU603127MMU Entry Numbers for APP CPU603128MMU Entry Numbers for PRO CPU (Special Mode)604129MMU Entry Numbers for APP CPU (Special Mode)604130Virtual Address Mode for External SRAM605131Virtual Address for External SRAM ( Normal Mode )606132Virtual Address for External SRAM ( Low-High Mode )606133Virtual Address for External SRAM (Even-Odd Mode)606134MMU Entry Numbers for External RAM607135MPU for Peripheral608136DPORT AHBLITE MPU TABLE X REG609137Interrupt Vector Entry Address611138Configuration of PIDCTRL LEVEL REG611139Configuration of PIDCTRL FROM n REG612141ESP32 Capacitive Sensing Touch Pads620142Inputs of SAR ADC module623143ESP32 SAR ADC Controllers624144Fields of the Pattern Table Register626145Fields of Type I DMA Data Format627146Fields of Type II DMA Data Format627149ALU Operations Among Registers649150ALU Operations with Immediate Value650151ALU Operations with Stage Count Register651152Input Signals Measured Using the ADC Instruction655155RTC Power Domains677156Wake-up Source679Espressif Systems18Submit Documentation FeedbackESP32 TRM (Version 4.6)

List of FiguresList of Figures1System Structure252System Address Mapping253Cache Block Diagram304Interrupt Matrix Structure345System Reset396System Clock407IO MUX, RTC IO MUX and GPIO Matrix Overview458Peripheral Input via IO MUX, GPIO Matrix469Output via GPIO Matrix4810ESP32 I/O Pad Power Sources (QFN 6*6, Top View)5111ESP32 I/O Pad Power Sources (QFN 5*5, Top View)5112DMA Engine Architecture11213Linked List Structure11314Data Transfer in UDMA Mode11415SPI DMA11516SPI Architecture11717SPI Master and Slave Full-duplex/Half-duplex Communication11818SPI Data Buffer12019GP-SPI 12320Parallel QSPI12321Communication Format of Parallel QSPI12422SDIO Slave Block Diagram15123SDIO Bus Packet Transmission15224CMD53 Content15225SDIO Slave DMA Linked List Structure15326SDIO Slave Linked List15327Packet Sending Procedure (Initiated by Slave)15428Packet Receiving Procedure (Initiated by Host)15529Loading Receiving Buffer15630Sampling Timing Diagram15631Output Timing Diagram15732SD/MMC Controller Topology18333SD/MMC Controller External Interface Signals18434SDIO Host Block Diagram18435Command Path State Machine18636Data Transmit State Machine18637Data Receive State Machine18738Descriptor Chain18939The Structure of a Linked List18940Clock Phase Selection19341Ethernet MAC Functionality Overview21342Ethernet Block Diagram21543MII Interface222Espressif Systems19Submit Documentation FeedbackESP32 TRM (Version 4.6)

List of Figures44MII Clock22345RMII Interface22446RMII Clock22547RMII Timing - Receiving Data22548RMII Timing – Transmitting Data22649Transmit Descriptor22650Receive Descriptor23251I2C Master Architecture27952I2C Slave Architecture27953I2C Sequence Chart28054Structure of The I2C Command Register28155I2C Master Writes to Slave with 7-bit Address28256I2C Master Writes to Slave with 10-bit Address28357I2C Master Writes to addrM in RAM of Slave with 7-bit Address28458Master Writes to Slave with 7-bit Address in Three Segments28559Master Reads from Slave with 7-bit Address28660Master Reads from Slave with 10-bit Address28761Master Reads N Bytes of Data from addrM in Slave with 7-bit Address28762Master Reads from Slave with 7-bit Address in Three Segments28863I2S System Block Diagram30264I2S Clock30465Philips Standard30566MSB Alignment Standard30567PCM Standard30668Tx FIFO Data Mode30769The First Stage of Receiving Data30870Modes of Writing Received Data into FIFO30971PDM Transmitting Module31072PDM Sends Signal31173PDM Receives Signal31174PDM Receive Module31175LCD Master Transmitting Mode31276LCD Master Transmitting Data Frame, Form 131377LCD Master Transmitting Data Frame, Form 231378Camera Slave Receiving Mode31379ADC Interface of I2S031480DAC Interface of I2S31481Data Input by I2S DAC Interface31482UART Basic Structure33783UART Shared RAM33884UART Data Frame Structure33985AT CMD Character Format33986Hardware Flow Control34087LED PWM Architecture37888LED PWM High-speed Channel Diagram37889LED PWM Divider379Espressif Systems20Submit Documentation FeedbackESP32 TRM (Version 4.6)

List of Figures90LED PWM Output Signal Diagram38091Output Signal Diagram of Fading Duty Cycle38092RMT Architecture39493Data Structure39594MCPWM Module Overview40395Prescaler Submodule40596Timer Submodule40597Operator Submodule40698Fault Detection Submodule40899Capture Submodule408100Count-Up Mode Waveform409101Count-Down Mode Waveforms410102Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event410103Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event410104UTEP and UTEZ Generation in Count-Up Mode411105DTEP and DTEZ Generation in Count-Down Mode412106DTEP and UTEZ Generation in Count-Up-Down Mode412107Submodules Inside the PWM Operator414108Symmetrical Waveform in Count-Up-Down Mode418109Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA andPWMxB — Active High419110Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA420111Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and112Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA andPWMxB — Active High421PWMxB — Complementary422113Example of an NCI Software-Force Event on PWMxA423114Example of a CNTU Software-Force Event on PWMxB424115Options for Setting up the Dead Time Generator Submodule426116Active High Complementary (AHC) Dead Time Waveforms427117Active Low Complementary (ALC) Dead Time Waveforms428118Active High (AH) Dead Time Waveforms428119Active Low (AL) Dead Time Waveforms429120Example of Waveforms Showing PWM Carrier Action431121Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule 432122Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule433123PULSE CNT Architecture485124PULSE CNT Upcounting Diagram487125PULSE CNT Downcounting Diagram487126The bit fields of Data Frames and Remote Frames531127Various Fields of an Error Frame533128The Bit Fields of an Overload Frame534129The Fields within an Interframe Space536130Layout of a Bit537131TWAI Overview Diagram539132Acceptance Filter547Espressif Systems21Submit Documentation FeedbackESP32 TRM (Version 4.6)

List of Figures133Single Filter Mode548134Dual Filter Mode549135Error State Transition550136Positions of Arbitration Lost Bits552137Noise Source588138Flash Encryption/Decryption Module Architecture590139MMU Access Example598140Interrupt Nesting613141Touch Sensor619142Touch Sensor Structure620143Touch Sensor Operating Flow621144Touch FSM Structure622145SAR ADC Depiction622146SAR ADC Outline of Function623147RTC SAR ADC Outline of Function625148Diagram of DIG SAR ADC Controllers626149Hall Sensor628150Diagram of DAC Function629151Cosine Waveform (CW) Generator630152ULP Coprocessor Diagram647153The ULP Coprocessor Instruction Format648154Instruction Type — ALU for Operations Among Registers649155Instruction Type — ALU for Operations with Immediate Value650156Instruction Type — ALU for Operations with Stage Count Register650157Instruction Type — ST651158Instruction Type — LD651159Instruction Type — JUMP652160Instruction Type — JUMPR652161Instruction Type — JUMP653162Instruction Type — HALT653163Instruction Type — WAKE654164Instruction Type — SLEEP654165Instruction Type — WAIT654166Instruction Type — ADC655167Instruction Type — I²C655168Instruction Type — REG RD656169Instruction Type — REG WR657170Control of ULP Program Execution658171Sample of a ULP Operation Sequence659172I²C Read Operation660173I²C Write Operation661174ESP32 Power Control671175Digital Core Voltage Regulator672176Low-Power Voltage Regulator673177Flash Voltage Regulator674178Brownout Detector674Espressif Systems22Submit Documentation FeedbackESP32 TRM (Version 4.6)

List of Figures179RTC Structure675180RTC Low-Power Clocks676181Digital Low-Power Clocks676182RTC States677183Power Modes679184ESP32 Boot Flow681Espressif Systems23Submit Documentation FeedbackESP32 TRM (Version 4.6)

1 System and Memory1 System and Memory1.1 IntroductionThe ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory, externalmemory and peripherals are located on the data bus and/or the instruction bus of these CPUs.With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that theyuse the same addresses to access the same memory. Multiple peripherals in the system can access embeddedmemory via DMA.The two CPUs are named “PRO CPU” and “APP CPU” (for “protocol” and “application”), however, for most purposes the two CPUs are interchangeable.1.2 Features Address Space– Symmetric address mapping– 4 GB (32-bit) address space for both data bus and instruction bus– 1296 KB embedded memory address space– 19704 KB external memory address space– 512 KB peripheral address space– Some embedded and external memory regions can be accessed by either data bus or instruction bus– 328 KB DMA address space Embedded Memory– 448 KB Internal ROM– 52

13.3.6.1 Hardware Flow Control 340 13.3.6.2 Software Flow Control 341 13.3.7 UART DMA 341 13.3.8 UART Interrupts 341 13.3.9 UHCI Interrupts 342 13.4 Register Summary 343 13.4.1 UART Registers 343 13.4.2 UHCI Registers 344 13.5 Registers 346 14 LED PWM Controller (LEDC) 378 14.1 Introduction 378 Espressif